The Present invention relates to semiconductor devices and more particularly to a semiconductor device having an integrated circuit including therein a metal film resistance.
Resistance elements constitute an important part of analog integrated circuit.
Particularly, a resistance element of a metal thin-film (called hereinafter as metal thin-film resistance) attracts attention in view of its small temperature dependence of the resistance value (TCR).
For the material of such metal thin-film resistance, chromium-silicon (CrSi), nickel chromium (NiCr), tantalum nitride (TaN), chromium silicide (CrSi2), chromium silicide nitride (CrSiN), chromium silicon oxy (CrSiO), and the like, are used.
With a semiconductor device having such a metal thin-film resistance, it is generally practiced to form the metal thin-film resistance with very small thickness of 1000 Angstroms or less in order to meet for the demand of high integration density and for higher sheet resistance.
Conventionally, following methods are known for achieving electrical connection with a metal thin-film resistance:
1) Directly connecting a metal interconnection pattern to the metal thin-film resistance (Patent Reference 1);
2) Forming an interlayer insulation film after formation of the metal thin-film resistance; forming a contact hole in the interlayer insulation film; and connect a metal interconnection via the foregoing contact hole (Patent Reference 2 and Patent Reference 3).
3) Forming a barrier layer on the metal thin-film resistance and connecting a metal interconnection to such a barrier film (Patent Reference 4 and Patent Reference 5); and
4) Forming an electrode in a contact hole formed in an insulation film, forming a resistance film on the insulation film, and forming a pattern of the resistance body by applying an anisotropic etching process to the resistance film such that the resistance pattern makes a contact with the electrode (Patent Reference 1).
Hereinafter, the method of achieving electrical connection to the metal thin-film resistance of the prior art 1)-4) above will be explained with reference to FIG. 42.
1) Referring to FIG. 42, the method of forming a metal interconnection directly on the metal thin-film resistance will be explained.
First, a first interlayer insulation film 5 is formed on a silicon substrate 1 still in the form of wafer but already formed with a device isolation oxide 3 and transistors (not illustrated), and a metal thin-film resistance 101 is formed on the first layer interlayer insulation film 5. Further, a metal film is formed on the entire surface of the first layer interlayer insulation film 5 including the metal thin-film resistance 101 for the purpose of interconnection, and a first layer metal interconnection pattern 103 is formed by patterning the metal film by using a wet etching process.
Here, it should be noted that, in the general fabrication process of semiconductor devices, a dry etching process is used for etching a metal film for formation of interconnection pattern, while in the present case, there exists a metal thin film resistance 101 of small film thickness right underneath the metal film to be patterned, and thus, it is not possible to use the dry etching process, as such a dry etching process causes etching of the metal thin film resistance 101 at the time of the overetching process. Thus, there is a need of forming the first layer metal interconnection pattern 103 by patterning the metal film for interconnection by using a wet etching process.
2) Next, with reference to FIG. 43, the method of forming an interlayer insulation film after formation of the metal thin-film resistance and connecting a metal interconnection by forming a contact hole in such an interlayer insulation film will be explained.
In this process, the device isolation oxide 3 the first interlayer insulation film 5 and the metal thin-film resistance 101 are formed on a silicon substrate 1, and a CVD (chemical vapor deposition) oxide film 105 is formed on the first layer interlayer insulation film 5 including the metal thin-film resistance 101 as an interlayer insulation film to the metal interconnection. Further, a resist pattern having a resist opening in correspondence to both end parts of the metal thin-film resistance 101 is formed on the CVD oxide film 105 for formation of the contact hole used for connection to metal interconnection patterns, and the CVD oxide film 105 is removed selectively by a wet etching process while using the resist pattern as a mask, to form a contact hole 107. After removal of the resist pattern, a metal film of AlSiCu for interconnection is formed on the CVD oxide film 105 so as to include the contact hole 107. By patterning the metal film, a first layer metal interconnection pattern 109 is formed.
In general fabrication process of semiconductor devices, a dry etching process is used generally for formation of such a contact hole 107. In the case in which the thickness of the metal thin-film resistance 101 is smaller than 1000 Angstroms, however, it is difficult to prevent the contact hole 107 to penetrate through the thin metal thin-film resistance 107, and thus, it is necessary to use a wet etching process for the formation of the contact hole 107.
3) Next, the method of forming a barrier film on a metal thin-film resistance and connect a metal interconnection so such a barrier film will be explained with reference to FIG. 44.
Referring to FIG. 44, the device isolation oxide 3, the first layer interlayer insulation film 5 and the metal thin-film resistance 101 are formed on the silicon substrate 1, and a refractory metal film such as TiW is formed on the first interlayer insulation film 5 including the metal thin-film resistance 101 as a barrier film to the metal interconnection pattern. Thereafter, a metal film for interconnection is formed thereon, and the first layer metal interconnection pattern 111 is formed by patterning the metal film for interconnection by using a dry etching process. Because of the existence of the refractory metal film underneath the interconnection metal film, there arises no problem that the metal thin-film resistance 101 undergoes etching even when a dry etching process is used for the patterning of the metal interconnection pattern 111.
Thereafter, a wet etching process is used to remove the refractory metal film selectively by using the first layer metal interconnection pattern 111 as a mask, and there is formed a refractory metal film pattern 113. In this step of patterning of the foregoing refractory metal film, it should be noted that the use of dry etching process is difficult in view of the existence of the refractory metal film immediately on the metal thin-film resistance 101.
4) Next, the process of forming electrode in a contact hole in an insulation film and forming a resistance pattern by forming a resistance film on the insulation film and patterning the same by a dry etching process in contact with the electrode will be explained with reference to FIG. 45. In the example explained with reference to FIG. 45, a metal interconnection pattern is formed further on the metal interconnection pattern formed underneath the contact hole.
Referring to FIG. 45, the first layer interlayer insulation film 5 is formed on the silicon substrate 1 and a first layer metal interconnection pattern 115 is formed on the first layer metal interlayer insulation film 5.
After formation of an insulation film 117 on the first interlayer insulation film 5, a first contact hole 119 is formed in the insulation film 117 formed on the first layer metal interconnection pattern 115 in correspondence to both ends of the metal thin-film resistance, and a conductive plug (electrode) 121 is formed by filling the first contact hole 119 with a conductive material. In this step, it should be noted that no contact hole is formed for electrical connection with a second layer metal interconnection pattern to be formed later.
Next, a metal film for metal thin-film resistance is formed on the entire surface of the insulation film 117, and the metal thin-film resistance 101 is formed on the conductive plug 121 and the insulation film 117 by patterning the metal film.
Further, an insulation film 123 is formed on the entire surface of the insulation film 117 so as to prevent etching of the metal thin-film resistance 101 at the time of patterning the second metal interconnection pattern to be later by using a dry etching process. Further, a second contact hole 125 is formed in the insulation films 117 and 123 on the first layer metal interconnection pattern in an area different from the area where the metal thin-film resistance 101 is formed for electrical connection with the second layer metal interconnection pattern. Further, a second conductive plug 127 is formed by filling the second contact hole with a conductive material. Further, a metal film for the second layer metal interconnection is formed on the insulation film 123 so as to include the region where the second conductive plug 127 is formed, and the metal film is patterned by a photolithographic process and dry etching process to form a second layer metal interconnection pattern 129 on the second conductive plug 127 and the insulation film 123.
Further, there is disclosed a semiconductor integrated circuit device equipped with a resistance, although not a thin-film resistance, formed on the uppermost interconnection electrode via an insulation film in electrical connection with the foregoing uppermost interconnection electrode (reference should be made to Patent Reference 6, for example).
Referring to FIG. 46, a hypothetical case in which such a structure is applied to a metal thin-film resistance is explained.
Referring to FIG. 46, the first interlayer insulation film 5 is formed on the silicon substrate 1 carrying the device isolation oxide 3, and after formation of the first layer metal interconnection pattern 115 on the first layer interlayer insulation film 5, an underlying insulation film 131 is formed on the entire surface of the first interlayer insulation film 5 including the first layer metal interconnection pattern 115. Further, a contact hole 133 is formed in the underlying insulation film 131 on the first metal interconnection pattern 115 by using a photolithographic process and a dry etching process. Further, a metal thin-film for the metal thin-film resistance is formed on the entire surface of the underlying insulation film 131 including the region where the contact hole 133 is formed, and the metal thin-film resistance 101 is formed by patterning the metal thin-film in a predetermined shape.
Further, there is a disclosure of a semiconductor integrated circuit carrying a metal thin-film resistance on an insulation film, wherein the contact between the metal thin film resistance and the metal interconnection in the electrode part of the metal thin-film resistance is achieved in an end part and at least a top part of the terminal region of the metal interconnection (reference should be made to Patent Reference 7).
Referring to FIG. 47, the method of achieving electrical contact between the metal thin-film resistance and the metal interconnection at the end part and at least a part of the top surface of the metal interconnection will be explained.
Referring to FIG. 47, the first interlayer insulation film 5 is formed on the silicon substrate 1 carrying the device isolation oxide film 3, and the first metal interconnection pattern 115 is formed on the first interlayer insulation film 5. Further, a plasma nitride film 135 is formed on the entire surface of the first interlayer insulation film 5 including the first layer metal interconnection pattern 115, and the end part and a part of the to surface of the first layer metal interconnection pattern are exposed by removing a part of the plasma nitride film 135. Thereafter, a metal thin film for the metal thin-film resistance is deposited by evaporation deposition process, and the metal thin-resistance 101 is formed by patterning the metal thin-film thus formed.
Further, a laser trimming process is conducted generally in semiconductor devices after completion of the physical structure thereof for trimming of performance thereof, by irradiating a laser beam to fuse or resistance elements therein for disconnection or modification (reference should be made to Patent Reference 8).
However, with such a laser trimming process, there has been a problem, upon irradiation of the semiconductor substrate such as a silicon substrate via an insulation film such as a silicon oxide film with the laser beam, in that the irradiated laser beam causes damages in the insulation film or silicon substrate and the reliability of the semiconductor device is degraded. Further, there has been a problem, in the trimming process called on-line trimming in which trimming is conducted while measuring the performance of the semiconductor device, in that electron-hole pairs are induced in the silicon substrate as a result of irradiation of the laser beam upon the silicon substrate. Such electron-hole pairs cause noise at the time of performance measurement, and it has been difficult to carry out precise trimming.
In order to minimize such problems there have been various proposals such as disposing a film opaque to the laser beam around the resistance element (reference should be made to Patent Reference 9) or disposing a laser beam shield of polysilicon, refractory metal or refractory metal silicide between a fuse of polysilicon and a silicon substrate (reference should be made to Patent Reference 10).
Further, Patent Reference 1 discloses a structure in which at least a part of the resistance is formed in the region where the semiconductor device is formed.